1. Field of the Invention
The present invention relates to an instruction issuing device which controls the issue of an instruction to a plurality of arithmetic units of different types, and issues an instruction to a suitable issue destination.
2. Description of the Related Art
In a processor having a plurality of arithmetic units whose feasible operation types are different, there may be cases where an instruction that can be issued only to an arithmetic unit of a particular type, and an instruction that can be issued to arithmetic units of several types coexist. In the processor having such an architecture, the issue destination of an instruction is determined by an issue controlling circuit.
FIG. 1A shows the issue control performed by a conventional issue controlling circuit. For ease of explanation, considered here is the case where four instructions can be simultaneously issued, and an arithmetic unit that performs an operation of a type A and an arithmetic unit that performs an operation of a type B exist.
In FIG. 1A, an issue latch 1 comprises 4 instruction slots for holding fetched instructions. An issue controlling circuit 2 controls the issue of the instructions held by the issue latch 1 xe2x80x9cin orderxe2x80x9d. Reservation stations 3 and 4 respectively comprise a plurality of instruction slots for holding the entries of instruction waiting to be processed, and passes the entries to arithmetic units 5 and 6 xe2x80x9cout of orderxe2x80x9d.
Here, xe2x80x9cin orderxe2x80x9d means that instructions are processed in an order directed by a program, whereas xe2x80x9cout of orderxe2x80x9d means that instructions are processed in an order different from that directed by a program.
The arithmetic unit 5 performs an operation of a type A, and the reservation station 3 holds the entries of instructions that can be executed by the arithmetic unit 5. In the meantime, the arithmetic unit 6 performs an operation of a type B, and the reservation station 4 holds the entries of instructions that can be executed by the arithmetic unit 6.
The issue controlling circuit 2 performs a control for preferentially selecting the arithmetic unit of the type A as an issue destination of an instruction, and issues to the arithmetic unit 5 an instruction (any instruction) that can be issued to both of the types A and B as far as possible.
With such a control, an any instruction is issued to the arithmetic unit 5 of the type A in a fixed manner if this instruction is included as a first instruction (Slot 0) or a second instruction (Slot 1) in the issue latch 1. Additionally, if the any instruction is included as a third (Slot 2) or subsequent instruction, and if an empty quantity (the number of empty slots) of the reservation station 3 of the type A is 0, this instruction is issued to the arithmetic unit 6 of the type B.
In FIG. 1A, the empty quantities of the reservation stations 3 and 4 are respectively 1 and 2, and an any instruction, A instruction, B instruction, and other instruction are respectively held in Slots 0 through 3 of the issue latch 1. The A instruction is an instruction that can be issued only to the arithmetic unit of the type A. The B instruction is an instruction that can be issued only to the arithmetic unit of the type B.
At this time, since the first any instruction is issued to the arithmetic unit 5 in a fixed manner, the empty quantity of the reservation station 3 results in 0. Therefore, the issue controlling circuit 2 waits until the slot of the reservation station 3 becomes empty, and issues the second A instruction to the arithmetic unit 5.
FIG. 1B shows an issue stage of instruction pipeline processing. This issue stage is composed of two durations T1 and T2. The issue controlling circuit 2 determines the issue destination of an instruction in consideration of a preferential issue destination in the duration T1, and performs a postprocess in the duration T2 after the issue destination is determined.
However, because the issue controlling circuit 2 shown in FIG. 1A issues instructions in order, it cannot issue the third and subsequent instructions until the second A instruction is issued, although the reservation station 4 of the type B has an empty slot.
As described above, if the number of empty slots for an arithmetic unit at a preferential issue destination becomes small when the issue controlling circuit whose preferential issue destination is predetermined, the number of instructions that can be simultaneously issued becomes small.
Therefore, a method selecting the issue destination of an any instruction from among a plurality of arithmetic units without predetermining a preferential issue destination is considered. In this case, to determine the optimum issue destination of the any instruction, it is necessary to calculate the empty quantities of slots of the plurality of arithmetic units, and to select an issue destination which maximizes the number of instructions that can be simultaneously issued.
FIG. 1C shows the issue stage in which such a control is performed. This issue stage includes a duration T3 corresponding to a newly added determining circuit in addition to the durations T1 and T2 shown in FIG. 1B. This determining circuit calculates the empty quantities of slots of a plurality of arithmetic units, and determines an optimum preferential issue destination at that time. The issue controlling unit performs the operations of the durations T1 and T2 based on the determined preferential issue destination.
However, considering the empty quantities of a plurality of reservation stations and the types of instructions, the number of their combinations is very large. Therefore, it is difficult to quickly obtain an optimum solution in one pipeline stage. If the issue destination of each instruction is strictly determined, the operations in the durations T1 and T3 become more complicated, so that the time required for one stage becomes long and the processing speed is deteriorated.
An object of the present invention is to provide an instruction issuing device which can determine, for a relatively short time, an issue destination which maximizes the number of instructions that can be simultaneously issued.
An instruction issuing device according to the present invention comprises a plurality of issue controlling circuits, a comparing circuit, a learning circuit, a register circuit, a selecting circuit and an issuing circuit.
The issue controlling circuit performs a control for preferentially issuing an instruction (any instruction) that can be issued to any of a plurality of arithmetic units which perform operations of different types, and determine an issue destination arithmetic unit in parallel. Especially, if a given instruction is an any instruction, each of the issue controlling circuits specifies an arithmetic unit at a preferential issue destination as an issue destination. As a result, a plurality of issue destinations are independently determined for the single given instruction.
In a first aspect of the present invention, a comparing circuit makes a comparison among the empty quantities of instruction slots for a plurality of arithmetic units, and outputs a result of the comparison. A selecting circuit selects one of the plurality of issue controlling circuits based on the result of the comparison. The issuing circuit issues an instruction to an issue destination arithmetic unit specified by the selected issue controlling circuit.
In a second aspect of the present invention, a learning circuit learns a preferential issue destination according to a pattern of an instruction sequence to be issued, and stores learning information indicating the preferential issue destination. The selecting circuit selects one of a plurality of issue controlling circuits based on the learning information. The issuing circuit issues an instruction included in the instruction sequence to the issue destination arithmetic unit specified by the selected issue controlling circuit.
In a third aspect of the present invention, a register circuit stores preferential issue destination information specified by a register write instruction. A selecting circuit selects one of a plurality of issue controlling circuits based on the preferential issue destination information. The issuing circuit issues an instruction to the issue destination arithmetic unit specified by the selected issue controlling circuit.